The present invention relates to an integrated circuit and, more particularly, to a gated flip-flop circuit.
In general, digital logic systems are classified as a combinational circuit and a sequential circuit. The combination circuit comprises logic gates whose outputs are directly determined by current input values. The combination circuit performs a specific information processing operation logically specified by a series of Boolean expressions. The sequential circuit uses storage devices called as a flip-flop, in addition to the logic gates. Outputs of the storage devices are functions of inputs and states of storage devices. The states of the storage devices are functions of the previous inputs. Consequently, the outputs of the sequential circuit depend on previous values as well as current values, and the operation of the sequential circuit is characterized by a time sequence of the inputs and the inner states thereof.
All of the digital systems have combinational circuits, but almost all of the real systems comprise storage devices such as latches. The digital circuits using the latches are, for example, registers, counters, and static memory arrays, and so on. Therefore, to implement a high-speed low-power digital system, it is important, among other things, to effectively design flip-flops significantly related to a speed or a power of the digital system.
Typically, the speed of the flip-flop is determined by a DtoQ time. The DtoQ time can be represented as described below. As is well known, a setup time should be sufficiently assigned to latch data into the flip-flop in a stable manner. The setup time is indicated by tSETUP of FIG. 1. Data inputted in synchronization with a rise edge of a clock signal CLK is outputted as output data Dout after a predetermined time, which is indicated by tCtoQ of FIG. 1. Therefore, the DtoQ time (tDtoQ) to determine the speed of the flip-flop can be represented as a summation of the tSETUP and the tCtoQ.
For the recent digital system, it is quite important to improve the speed of the flip-flop as well as implement the low-power flip-flop. To meet these requirements, a gated flip-flop has been proposed. As is well known to those skilled in the art, the gated flip-flop is configured to operate only for an activation period of a control signal, which is called as an “enable signal”. An exemplary gated flip-flop circuit is shown in FIG. 2. Referring to FIG. 2, a gated flip-flop circuit 1 latches data D in synchronization with a clock signal CK for the activation period of the enable signal EN, and outputs the latched data as output data Q. For the gated flip-flop circuit 1 shown in FIG. 2, the clock signal CK is not directly applied to a data transmission path (path comprising inverters 19, 20, 21, 22, 23 and 24) of the flip-flop circuit 1, but a gated clock signal GCK, or a combination of the clock signal CK and the enable signal EN, is applied to the data transmission path of the flip-flop circuit 1.
The speed of the gated flip-flop circuit 1 described above depends on the DtoQ time as well as the EtoQ time. This is because the clock signal is not directly applied to the data transmission path but the gate clock signal, or a combination of the clock signal and the enable signal, is applied to the data transmission path. Here, the EtoQ time refers to a delay time from the activation time of the enable signal EN to a data output time. As shown in FIG. 2, the transmission path of the gated flip-flop circuit (10, 11, 12, 13, 14, 15, 16, 17 and 18) determines the EtoQ time. Likewise, since the speed of the gated flip-flop circuit is determined by the DtoQ time as well as the EtoQ time, it is desirable to reduce the DtoQ time and the EtoQ time to implement a high-speed and low-power gated flip-flop circuit.